1. Field of the Invention.
This invention relates to the field of semiconductor integrated circuits, and particularly to an improvement in constructing an on chip power supply bypass capacitor to suppress transient voltage spikes.
2. Description of the Related Art
Capacitance bypassing of an integrated circuit's power supply nodes is typically done in moderate to high speed applications in order to filter out transient voltage spikes which are a consequence of transient current flow due to logic switching. With larger die sizes and smaller geometry transistors current transients on integrated circuits have been increasing in magnitude as the technology evolves. Even the small inductance of package leads, bond wires, and chip interconnect wires causes an unacceptable amount of voltage spiking or bouncing which has a disruptive effect on logic and analog integrated circuits.
Capacitors can be placed on a printed circuit board near the integrated circuit's power pins, Vss and Vdd, but the transient suppression is limited by lead and bond wire inductance. Capacitors can also be placed in a package along side the chip die but bond wire inductance limits performance. U.S. Pat. No. 5,629,240 a means is described of attaching a power supply bypass capacitor directly on to a chip in order to reduce parasitic inductance.
The most ideal capacitor associated with chip power bus bypassing is one which distributes the capacitance over the chip's power supply lines or wires and, correspondingly, offers very little parasitic inductance. With a large distributed "on` chip capacitor it is possible to reduce the number of power pins since multiple power pins for a given power bus are largely a consequence of the need to reduce package pin and bond wire inductance. Another desirable quality of a large distributed power bus bypass capacitor is to improve Electrostatic Discharge (ESD) protection when pad diode clamps to ground and power are used.
There are patents that describe "on" chip means to build ground to power bus capacitors including MOS capacitors and metal-insulator-metal capacitors. U.S. Pat. No. 4,937,649 a metal-insulator-metal capacitor is described in which one level of metal is used for both ground routing and as a bypass capacitor plate and a second level of metal is used for power routing and as the second bypass capacitor plate. The disadvantage of this scheme is that it requires more than two additional masking steps in order to create the two metal levels and the metal connections to the lower levels of metal in a multi-metal integrated circuit.